There has been a general trend in the reduction in size of micro-electronic systems. Chip scale packaging, flip chips, and multichip modules are generally applied to a variety of electronic product categories such as mobile phones, hand-held computers, chip cards, and similar applications/devices. Future applications of electronic devices may require relatively complicated elements supporting various functions, which often results in the chip area being required to be relatively large to meet demands. This results in challenges with manufacturing yield of chips due to an integration of multifunctional devices, an increase in cost due to complexity of device implementation, and technical limitations. In addition, wirings between subsystems may be challenging due to limitations in performance, multifunctionality, reliability and similar issues of micro-electronic systems. These factors may be critical performance bottlenecks for future integrated circuit generation. A 3D integration technology may have significant potential to replace an embedded system on chip (SoC) technology.
In a packaging process, a super-contact hole may serve as a pad and a normal contact hole may serve for connecting wirings that are simultaneously patterned on a single wafer. The super-contact hole may have a diameter ranging from approximately 1 μm to 2 μm and a depth ranging from approximately 6 μm to 10 μm. A non-super-contact hole may have a diameter ranging from approximately 0.1 μm to 0.3 μm and a depth ranging from approximately 1 μm to 2 μm.
A process of forming a related art super-contact can be described with reference to FIGS. 1A to 1E. Example FIGS. 1A to 1E are cross-sectional views illustrating a process of forming a super-contact, according to the related art. As shown in example FIG. 1A, an device isolation layer (not shown) may define an active region. Unit elements (such as a PMOS transistor and an NMOS transistor including a source/drain junction part and a gate 50 formed on the active region and similar elements) may be formed on a semiconductor substrate 100.
As shown in FIG. 1B, an interlayer dielectric layer 102 may be formed on the entire structure with the unit elements formed thereon. A photoresist pattern 104 for a super-contact hole may be formed on the interlayer dielectric layer 102. Then the interlayer dielectric layer 102 and the semiconductor substrate 100 may be etched by an etching process using the photoresist pattern 104 as an etching mask to form a super-contact hole 106.
As shown in FIG. 1C, the photoresist pattern 104 may be removed through a strip process, and an insulation film 108 may be formed on the surface of the entire structure including the super-contact hole 106. The insulation film 108 may serve as a shielding insulation film of a super-contact to be formed later and may be formed of at least one of oxide series and nitride series.
As shown in FIG. 1D, the super-contact hole 106 may be filled with a conductive material (e.g. tungsten (W)) to form a conductive layer 110. As shown in FIGS. 1D and 1E, a photoresist pattern 111 for a normal contact hole may be formed on an upper portion of the entire structure with the conductive layer 110 filled in the super-contact hole 106. The interlayer dielectric layer 102 may be etched through an etching process using the photoresist pattern 111 as an etching mask to form a normal contact hole 112. The photoresist pattern 111 for a normal contact is removed.
In the foregoing related art super-contact hole formation process, the insulation film 108 is formed after the formation of the super contact hole 106. However, the interlayer dielectric layer 102 may not be etched enough when forming the normal contact hole 112, which may cause problems with an electrical connection to the active region. For example, when the normal contact hole 112 is formed, since the interlayer dielectric layer 102 needs to be etched deeper due to the insulation film 108, a portion A in the interlayer dielectric layer 102 may not be etched enough, which may cause problems in the electrical connection to the active region.